1. Field of the Invention
The present invention relates to a level shift circuit, which is used for an FM frequency band prescaler in a radio receiver of the digital tuning type, for example, and shifts an output level of an ECL (Emitter Coupled Logic) into an input level of a CMOS (Complementary Metal Oxide Semiconductor) circuit.
2. Description of the Related Art
There has been known an ECL-CMOS level shift circuit of this type as shown in FIG. 1. The level shift circuit is described in "IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21, NO. 5, OCT. 1986, 13-ns, 500-mW, 64Kbit, ECL RAM Using HI-BICMOS Technology" KATSUMI OGIUE et al., FIG. 6.
To secure a normal operation of the circuit shown in FIG. 1, all of the MOS transistors Q1 to Q4 making up a level shifter must operate in a saturation region. In an actual integrated circuit, however, those transistors Q1 to Q4 sometimes operate outside the saturation region due to a variance of circuit element parameters caused in the manufacturing stage, and a variation in the power voltage, and the like. When those transistors operate outside the saturation region, the level shift circuit operation is instable, and a production yield of the IC containing the level shift circuit is degraded. In designing the level shift circuit which is stable against the parameter variance and the power voltage variation, it is a key point how a voltage range of the gate bias voltage to amplifier (input) MOS transistors Q1 and Q2 is set. The gate bias voltage range is determined depending on resistance of resistors R1 and R2 of the ECL receiver and current IA of constant current source 10. The resistance and current IA also are inevitably influenced by the parameter variance and the power voltage variation. Thus, the character varying factors exist not only in the level shifter but also in the ECL receiver. This fact makes the design of the ECL receiver intricate and difficult.